The present invention relates to a data processing device having an analog-to-digital (AD) conversion function, and more particularly to a technique for enhancing the degree of conversion bit precision (resolution) in small-signal operation with respect to an AD conversion range.
In Patent Documents 1 and 2 indicated below, there are disclosed techniques for acquiring AD conversion result data having a higher degree of bit precision than that of an AD converter circuit.
According to the Patent Document 1, an AD converter device is so arranged that an input voltage is compared with a voltage obtained through DA conversion of AD-converted data of the input voltage to determine a difference voltage, which is then amplified and converted to prepare AD-converted data. Through addition of these AD-converted data, it is allowed to provide AD conversion result data having a higher level of resolution than that of an AD converter circuit. For DA conversion in the AD converter device, a PWM-type DA converter is used to improve the linearity of DA conversion characteristic for the purpose of enhancing low-order bit precision in AD conversion. A PWM circuit section in the AD converter device generates and outputs a PWM signal having a duty factor corresponding to AD-converted data of a sample-and-hold voltage VA, and the PWM signal thus output is smoothed through a lowpass filter to provide an analog voltage VD. Then, in a differential amplifier, a difference voltage between the sample-and-hold voltage VA and the analog voltage VD is amplified through multiplication by “2 to the ‘n’-th power” for output therefrom, and under the direction of a control section, AD-converted data of the difference voltage thus amplified is synthesized with AD-converted data of the sample-and-hold voltage, thereby providing AD conversion result data having a resolution level that is higher by “n” bits than that of the AD converter circuit.
According to the Patent Document 2, it is intended to provide an AD converter circuit device wherein, using an AD converter circuit thereof, digital signals having the number of output bits larger than that of the AD converter circuit are produced. In operation of the AD converter circuit disclosed in the Patent Document 2, when an input signal to the AD converter circuit has a value higher than or equal to a predetermined point, the input signal is amplified by an amplifier circuit, and then the resultant amplified signal is converted to a “C”-bit digital signal through the AD converter circuit. Thereafter, through a latch circuit, the “C”-bit digital signal is converted to a “C+a/6”-bit digital signal, which is then output from the AD converter circuit via a data selector. Contrastingly, when an input signal has a value lower than the predetermined point, the input signal is amplified by the amplifier circuit, and then the resultant amplified signal is converted to a “C”-bit digital signal through the AD converter circuit in the same manner as mentioned above. Thereafter, through a data interpolating circuit, the “C”-bit digital signal is converted to a “C+a/6”-bit digital signal, which is then output from the AD converter circuit via the latch circuit and data selector.    Patent Document 1:
Japanese Unexamined Patent Publication No. 2001-102927    Patent Document 2:
Japanese Unexamined Patent Publication No. 2000-174622